Overview

Knowing that a design violates its specification is only the first step towards a correct system. The violation may be caused by a fault in the design, but also by an error in the specification or in the environment constraints. A designer needs to understand the violation and to locate and correct the fault that causes it. Industrial experience shows that fault localization and rectification take much more time, effort, and expense than fault detection. Also, debugging often takes place late in the design cycle, which makes it a high-risk activity that may, if not done quickly and correctly, delay the release of a product.

The workshop addresses the technologies and methodologies that need to be employed after verification has detected the presence of a bug, combining the efforts of the computer-aided verification and software engineering communities.

Program

• V&D program
• V&D accepted papers
• V&D pre-proceedings

Invited Talks

• Monday, August 21st, 08:30‑09:15
  John Moondanos (Future Formal Technologies Group, Logic Design Group, Intel)
  From Error to Error: Debugging in the Era of Multi-core Designs
• Monday, August 21st, 09:15‑10:00
  Alper Sen (Freescale Semiconductor Inc)
  Error Diagnosis in Equivalence Checking of High Performance Microprocessors
• Monday, August 21st, 11:30‑12:30
  Andreas Zeller (University of Saarbruecken)
  Where Do Bugs Come From? [pdf]
• Monday, August 21st, 16:30‑17:30
  Martin Rinard (MIT)
  Automated Techniques for Surviving Software Errors [ppt]

Program Committee

• Roderick Bloem (Graz University of Technology),
• Alex Groce (Laboratory for Reliable Software, Jet Propulsion Laboratory),
• John Moondanos (Future Formal Technologies Group, Logic Design Group, Intel),
• Marco Roveri (ITC-irst),
• Fabio Somenzi (University of Colorado at Boulder),
• Markus Stumptner (University of South Australia), and
• Andreas Zeller (University of Saarbruecken).