CADS 2020: 20th International Symposium on Computer Architecture and Digital Systems University of Guilan Rasht, Iran, August 19-20, 2020 |
Conference website | http://cads2020.guilan.ac.ir/ |
Submission link | https://easychair.org/conferences/?conf=cads20 |
Poster | download |
Proposals for Workshop | February 3, 2020 |
Submission deadline | May 31, 2020 |
The 20th International Symposium on Computer Architecture and Digital Systems (CADS’20) to be held on August 19-20, University of Guilan, Rasht, Iran. Previous date was April 22-23, Due to the COVID-19 pandemic, we are tentatively postponing the proceedings of CADS 2020 to be held on August 19-20. CADS is an annual Symposium providing an open forum for papers in broad field of computer architecture and digital systems.
Submission Guidelines
All papers must be original and not simultaneously submitted to another journal or conference. Papers must have a maximum of six pages, including references, appendices and figures, formatted according to the to IEEE Template Sponsored Conferences and Symposia, and must be submitted in electronic form (PDF format) through the Easy Chair submission site: http://cads2020.guilan.ac.ir/
List of Topics
- Computer Architecture, Processor Design, and Memory Systems
- Designing Electronics for the Internet of Things
- IoT Enabling Technologies
- Emerging Non-Volatile Memories and Solid-State Drives
- High-Performance I/O Systems and Storage System Architectures
- Parallel Processing and Multiprocessor Systems on Chip
- Dependable and Fault Tolerant System Designs
- Test, Verification, and Security of Digital Systems
- Emerging Technologies in VLSI
- Reconfigurable and FPGA Systems
- Architecture and Programming Support for Emerging Domains (Big Data, Deep Learning)
- Neuromorphic Computing
- Low Power and Energy Efficient Architectures
- Logic Synthesis and Electronic Design Automation
- Computer Arithmetic and Cryptography
- Interconnection Networks
- Network Processor Architectures
- Hardware Virtualization and Architecture Support for Operating Systems
- Parallel Algorithms, Tools for Hardware/ Software Design and Evaluation of Multicores
- Embedded and Cyber-Physical systems
- GPUs and other accelerator architectures
- Approximate Computing
Committees
Program Committee
- Hossein Asadi, Sharif University of Technology
- Amirali Baniasadi, University of Victoria
- Hassan Ghasemzadeh Mohammadi, Paderborn University
- Shaahin Hessabi, Sharif University of Technology
- Amir Hossein Jahangir, Sharif University of Technology
- Ali Jahanian, Shahid Beheshti University
- Farshad Khunjush, Shiraz University
- Somayyeh Koohi, Sharif University of Technology
- Pejman Lotfi-Kamran, Institute for Research in Fundamental Sciences (IPM)
- Amir Masoud Gharehbaghi, University of Tokyo
- Mehdi Modarressi, University of Tehran
- Alberto Nannarelli, Technical University of Denmark
- Behrooz Parhami, University of California at Santa Barbara
- Mehdi Saeedi, AMD
- Morteza Saheb Zamani, Amirkabir University of Technology
- Hamid Sarbazi-Azad, Institute for Research in Fundamental Sciences(IPM)
Organizing committee
- General Co-ChairsSeyed Ziauddin MirHosseini, University of GuilanSeyed Abolghasem Mirroshandel, University of Guilan
- Program ChairGhassem Jaberipur, Shahid Beheshti UniversityAssistant Program ChairHamidReza Ahmadifar, University of Guilan
- Local Arrangements & Financial ChairMahdi Aminian, University of Guilan
- Publication & Publicity ChairSeyed Mohammad Hossein Shekarian, University of Guilan
- Web, Registration and Workshop chairMohammad Salehi, University of Guilan
Invited Speakers
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Department of Electrical and Computer EngineeringUniversity of CaliforniaSanta Barbara, CA 93106-9560, USA
Title: Neurophysiological Discoveries of the 2014 Nobel Prize Winners in Medicine from a Computer Arithmetic Perspective
Abstract: The discovery that mammals use a multi-modular method akin to residue number system (RNS), but with continuous residues or digits, to encode position information led to the award of the 2014 Nobel Prize in Medicine. After a brief review of the evidence in support of this hypothesis, and how it relates to RNS, I discuss the properties of continuous-digit RNS, and discuss results on the dynamic range, representational accuracy, and factors affecting the choice of the moduli, which are themselves real numbers. I conclude with suggestions for further research on important open problems concerning the process of selection, or evolutionary refinement, of the set of moduli in such a representation.
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Professor & Director, IBM Centre for Advanced Studies - Atlantic
Faculty of Computer Science, University of New Brunswick -
Title:
Verilog-to-Routing: High Performance CAD and Customizable FPGA Architecture Modelling
Abstract:
In the face of both emerging and legacy application domains, and changes to manufacturing process technology, it is challenging to develop new Field Programmable Gate Array (FPGA) architectures. This is due in part to the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated Computer Aided Design (CAD) tools to target potential architectures. My talk will present version 8.0 of the open source Verilog-to-Routing (VTR) project, which provides such a design flow and can target a variety of FPGA architectures. In VTR 8 we have expanded the scope of FPGA architectures that can be modelled, giving FPGA architects more flexibility to customize their architectures, and enhanced the CAD flow for better interoperability with other tools. Together these enhancements allow VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both the validity of architectural conclusions and CAD algorithm comparisons, that VTR produce high-quality circuit implementations. In addition to presenting some of the new features of VTR 8.0, I will discuss some of the on-going research that we are performing on circuit optimization in the context of hard blocks and the trade-offs associated between speed and size when performing high-level synthesis.
Publication
CADS 2020 proceedings will be published in ...
Venue
The conference will be held in University of Guilan.
Contact
All questions about submissions should be emailed to cads2020@guilan.ac.ir or cads2020.guilan@gmail.com
Sponsors
IEEE Iran Section, Computer Society of Iran, University of Guilan