IWLS 2023: 32nd International Workshop on Logic & Synthesis EPFL Lausanne, Switzerland, June 5-6, 2023 |
Conference website | https://www.iwls.org/iwls2023/ |
Submission link | https://easychair.org/conferences/?conf=iwls2023 |
Abstract registration deadline | April 3, 2023 |
Submission deadline | April 10, 2023 |
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor. Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.
Submission Guidelines
Call for regular papers: Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants. The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Submissions are made electronically through EasyChair. Please see the workshop website for instructions: www.iwls.org.
Committees
Program Committee
- Luca Amaru, Synopsys, USA
- Anna Bernasconi, Università di Pisa, Italy
- Vinicius Callegaro, Siemens EDA, USA
- Sat Chatterjee, Google, USA
- Zhufei Chu, Ningbo University, China
- Valentina Ciriani, Università degli Studi di Milano, Italy
- Stephan Eggersglüß, Siemens EDA, Germany
- Petr Fišer, CTU, Czech Republic
- Jie-Hong Roland Jiang, National Taiwan University, Taiwan
- Victor Kravets, IBM, USA
- Walter Lau Neto, University of Utah, USA
- Giulia Meuli, Synopsys, Italy
- Alan Mishchenko, UC Berkeley, USA
- Augusto Neutzling, Cadence Design System, UK
- Weikang Qian, Shanghai Jiao Tong University, China
- Andre Reis, UFRGS, Brazil
- Heinz Riener, Cadence Design System, Germany
- Tsutomu Sasao, Meiji University, Japan
- Herman Schmit, Google
- Mathias Soeken, Microsoft, USA
- Eleonora Testa, Synopsys, USA
- Tiziano Villa, Università degli Studi di Verona, Italy
- Robert Wille, Johannes Kepler University, Austria
- Cunxi Yu, University of Utah, USA
Organizing Committee
- General Chair: Cunxi Yu, University of Utah, USA
- Program Committee Chairs: Xiaoqing Xu/Lana Josipovic, Google X, USA/ETH Zurich, Switzerland
- Program Contest Chair: Alan Mishchenko, University of California Berkeley, USA
- Special Session Chair: Eleonora Testa, Synopsys, USA
- Finance Chair: Zhufei Chu, Ningbo University, China
- Proceedings Chair: Walter Lau Neto, Univerisy of Utah, USA
- Publicity Chairs: Augusto Neutzling/Yingjie Li, Cadence, UK/University of Utah, USA
- Local Arrangements Chair: Siang-Yun Lee, EPFL, Switzerland