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Keyword:RISC-V

Papers
Simulation Based Evaluation of Bit-Interaction Side-Channel Leakage on RISC-V Processor
Tamon Asano and Takeshi Sugawara
In:Proceedings of 10th International Workshop on Security Proofs for Embedded Systems
Task Mapping and Scheduling in FPGA-Based Heterogeneous Real-Time Systems: a RISC-V Case-Study
Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler and Klaus McDonald-Maier
EasyChair Preprint no. 8979
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