Download PDFOpen PDF in browserRewriting Environment for Arithmetic Circuit Verification11 pages•Published: October 23, 2018AbstractThe paper describes a practical software tool for the verification of integer arithmetic circuits. It covers different types of integer multipliers, fused addmultiply circuits, and constant dividers  in general, circuits whose computation can be represented as a polynomial. The verification uses an algebraic model of the circuit and is accomplished by rewriting the polynomial of the binary encoding of the primary outputs (output signature), using the polynomial models of the logic gates, into a polynomial over the primary inputs (input signature). The resulting polynomial represents arithmetic function implemented by the circuit and hence can be used to extract functional specification from its gatelevel implementation. The rewriting uses an efficient AndInverter Graph (AIG) representation to enable extraction of the essential arithmetic components of the circuit. The tool is integrated with the popular ABC system. Its efficiency is illustrated with impressive results for integer multipliers, fused addmultiply circuits, and dividebyconstant circuits. The entire verification system is offered in an open source ABC environment together with an extensive set of benchmarks.Keyphrases: Arithmetic Circuits, computer algebra, formal verification In: Gilles Barthe, Geoff Sutcliffe and Margus Veanes (editors). LPAR22. 22nd International Conference on Logic for Programming, Artificial Intelligence and Reasoning, vol 57, pages 656666
