Explicit Conditional Discharge P Flip Flop Design in Nanometer Range

EasyChair Preprint no. 8014

Abstract

On the present scenario clock misalignment and power consumption are the most critical design problems facing by the designers. In fabricated design, the clock system composed of timing structure block such as flip flops and latches. In any logic design, clock interconnection is the most power consuming mechanism. The total power is consumed by the clock system is around 20-40% of total chip power [1]. Another impact of technology advancement is the new design issues. Scaling tends to emphasize several other deficiencies like introducing parasitic capacitances, delay due to interconnection wires and synchronization with circuit design [2]. The proposed design of flip flop reduces the transistor count and furthermore achieves improved speed and power performance. This objective is met by designing S-edit software of Tanner Tool. The simulation process is performed using 1.8 V supply voltage at 90nm CMOS technology.

Keyphrases: Clock cycle, conditional discharge, flip-flop, power dissipation

@Booklet{EasyChair:8014,
  author = {Rachana Arya and Bijoy Kumar Singh},
  title = {Explicit Conditional Discharge P Flip Flop Design in Nanometer Range},
  howpublished = {EasyChair Preprint no. 8014},

  year = {EasyChair, 2022}}