Dual-Material Gate Junctionless FET with Vertically Graded Channel Profile for Low Power Applications

EasyChair Preprint no. 7581

Abstract

The metal-oxide-semiconductor field-effect-transistor has dominated the semiconductor industry in the last four decades. To achieve more packaging density with higher speed the technological advancement has been impacted by the performance degradation of these conventional devices due to increased short channel effects namely subthreshold leakage current, subthreshold slope, drain induced barrier lowering etc. With simpler process steps and omission of p-n junctions the junctionless device has been used as an alternative to the ordinary MOSFETs for the low power applications in the nanoscale regime. This paper focus on the dual material gate junctionless FET with vertically graded profile. Comparable value of ON current, reduced OFF current, higher ON-to-OFF current ratio, and lower DIBL with improved subthreshold slope as compared to the conventional double gate junctionless FET with uniform doping profile have been reported.

Keyphrases: Dual Material, Graded Channel, Junctionless FET, low power

@Booklet{EasyChair:7581,
  author = {Sandeep Kumar and Arun Kumar Chatterjee and Rishikesh Pandey},
  title = {Dual-Material Gate Junctionless FET with Vertically Graded Channel Profile for Low Power Applications},
  howpublished = {EasyChair Preprint no. 7581},

  year = {EasyChair, 2022}}